ESL 架构建模工程师 薪资面议
上海-闵行区 5-10年 本科
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职位介绍
  • verilog
Job Description: As part of the ESL architecture team, engineer will mainly focus on following areas, but not limited to: 1. Architecture exploring for the complex SoC and high-speed subsystem include but not limited to memory, interconnection, ISP, GPU, CPU, and etc 2. Bring up the virtual platform and analysis the performance and power simulation result 3. Write the high quality SystemC/C++/TLM2 model for the memory, interconnection, and other high-speed subsystem 4. Work out the highly configurable work load model for the various components in various scenarios 5. Work out the SoC use case and performance goal in system level with help from product engineer 6. Assist design engineer to work out the ASIC micro-architecture 7. Co-work with verification engineer, design engineer, and software engineer to qualify and improve the quality of models. Job Requirements: 1. Degree in electrical engineering, computer engineering or related technical fields 2. Good knowledge of C++/SystemC modeling 3. Good knowledge on the Verilog and SystemVerilog. 4. A high-level of self-motivation and a proactive approach to solving problems Solid knowledge in one of the following areas is a plus: 1. Strong experience of high level modeling or software development with C++ 2. experience of the ASIC design or verification 3. Familiar with AMBA AXI/AHB/APB spec. 4. experience of GPU/VPU/DPU; 5. experience of PCIE/USB/Ethernet/UFS/eMMC; 6. Experience of low power design and power analysis; 7. Experience of complex SoC modeling
其他信息
所属部门:研发中心

公司简介

Siengine,芯擎科技, 是一家中外合资高科技公司,主要股东有亿咖通中国有限公司,安谋科技(中国)有限公司(ARM China)。亿咖通中国有限公司是吉利集团战略投资独立运营的全资子公司,ARM是全球芯片知识产权的知名企业。 Siengine致力于为汽车产业的未来发展提供技术先进的SOC解决方案,并成为一家全球化的高科技公司。 我们在上海、北京、武汉有运营办公室。
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